1. Field of the Invention
The present invention is related to a charge recycling circuit, and more particularly, to a charge recycling circuit for recycling charges which are discharged by a driving circuit and providing the recycled charges for charging the driving circuit.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in thin appearance, low power consumption and no radiation, have been widely used in electronic devices such as computers, mobile phones, and personal digital assistants (PDAs), etc. The amount of light transmission may be adjusted by changing the orientation of liquid crystal molecules, thereby enabling an LCD device to provide output light with various intensities, as well as red, green and blue light with various grayscales. An LCD device typically includes an LCD panel, a timing controller and a source driver. The timing controller is configured to generate data signal associated with display images, as well as control and timing signals for operating the LCD panel. The source driver is configured to generate driving signals of the LCD panel according to the data signals, the control signals and the timing signals.
Normally, the polarity of voltages applied to both sides of a liquid crystal layer needs to be inverted periodically to avoid permanent damages to the liquid crystal layer due to polarization and to reduce image sticking. Common LCD driving methods include frame inversion, line inversion and dot inversion. Therefore, the source driver needs to perform charging and discharging operations periodically for altering the polarity of the driving signals. Meanwhile, the output of the timing driver also needs to be switched between logic 1 and logic 0.
FIG. 1 is a diagram of a prior art driving circuit 10. The driving circuit 10 may be a source driver of an LCD device for converting an input voltage VIN into a plurality of output voltages VOUT1˜VOUTN. OP_O represents the unit gain buffer of all odd-numbered output channels, while OP_E represents the unit gain buffer of all even-numbered output channels (assuming N is a positive even number). The unit gain buffers OP_O and OP_E, coupled to a bias voltage VDD provided by a power supply, may be charged by the bias voltage VDD or discharged to a ground GND, thereby providing corresponding output voltages VOUT1˜VOUTN.
FIGS. 2A and 2B are signal diagrams of the prior art driving circuit 10 in operation. FIG. 2A illustrates the output waveforms of the unit gain buffers OP_O and OP_E when driven in a full-swing manner in which odd-numbered output voltages (the output voltage VOUT1 as an example) and even-numbered output voltages (the output voltage VOUT2 as an example) have opposite polarities during the same period. FIG. 2B illustrates the output waveforms of the unit gain buffers OP_O and OP_E when driven in a half-swing manner in which positive odd-numbered output voltages (the output voltage VOUT1 as an example) and negative even-numbered output voltages (the output voltage VOUT2 as an example) are provided during each period.
When operating the prior art driving circuit 10 in either full-swing or half-swing manner, the unit gain buffers OP_O and OP_E need to be charged by the bias voltage VDD for charging a loading capacitor and is configured to discharge the loading capacitor to the ground GND, thereby consuming a lot of power.